ST SPC560P34 - Page 107

RM0046 Clock Description
Doc ID 16912 Rev 5 107/936
The following values show the input setting for one possible configuration of the PLL:
● PLL input frequency: 4 MHz
● Loop divider (LDF): 64
● Input divider (IDF): 1
● VCO frequency = 4 MHz × 64 = 256 MHz
● PLL output frequency = 256 MHz/ODF
● Spread: Center spread (SPREAD_CONTROL = 0)
● Modulation frequency = 24 kHz
● Modulation depth = ±2.0% (4% pk-pk)
Using the formulae for MODPERIOD and INCSTEP:
Equation 3
MODPERIOD = Round [(4e06) / (4 × 24e03)] = Round [41.66] = 42
Equation 4
INCSTEP = Round [((2
15
– 1) × 2 × 64) / (100 × 5 × 42)] = Round [199.722] = 200
Equation 5
MODPERIOD × INCSTEP = 42 × 200 = 8400 (which is less than 2
15
)
Equation 6
md(quantized)% = ((42*200*100*5) / ((2^15-1)*64) = 2.00278% (peak)
Equation 7
Error in modulation depth = 2.00278 - 2.0 = 0.00278%
If we choose MODPERIOD = 41,
Equation 8
INCSTEP = Round [((2
15
– 1) × 2 × 64) / (100 × 5 × 41)] = Round [204.878] = 205
Equation 9
MODPERIOD × INCSTEP = 41 × 205 = 8405 (which is less than 2
15
)
Equation 10
md(quantized)% = ((41 × 205 × 100 × 5) / ((2
15
– 1) × 64) = 2.00397% (peak)
Equation 11
Error in modulation depth = 2.00397 – 2.0 = 0.00397%
The above calculations show that the quantization error in the modulation depth depends on
the flooring and rounding of MODPERIOD and INCSTEP. For this reason, the MODPERIOD
and INCSTEP should be judiciously rounded/floored to minimize the quantization error in
the modulation depth.