Mode Entry Module (MC_ME) RM0046
148/936 Doc ID 16912 Rev 5
S_PDO
Output power-down status — This bit specifies output power-down status of I/Os. This bit is
asserted whenever outputs of pads are forced to high impedance state or the pads power
sequence driver is switched off.
0 No automatic safe gating of I/Os used and pads power sequence driver is enabled
1 In SAFE/TEST modes, outputs of pads are forced to high impedance state and the pads power
sequence driver is disabled. The inputs are level unchanged. In STOP0 mode, only the pad
power sequence driver is disabled, but the state of the output remains functional.
S_MVR
Main voltage regulator status
0 Main voltage regulator is not ready
1 Main voltage regulator is ready for use
S_DFLA
Data flash availability status
00 Data flash is not available
01 Data flash is in power-down mode
10 Data flash is not available
11 Data flash is in normal mode and available for use
S_CFLA
Code flash availability status
00 Code flash is not available
01 Code flash is in power-down mode
10 Code flash is in low-power mode
11 Code flash is in normal mode and available for use
S_PLL0
system PLL status
0 system PLL is not stable
1 system PLL is providing a stable clock
S_XOSC0
4 MHz crystal oscillator status
0 4 MHz crystal oscillator is not stable
1 4 MHz crystal oscillator is providing a stable clock
S_16 MHz_IRC
16 MHz internal RC oscillator status
0 16 MHz internal RC oscillator is not stable
1 16 MHz internal RC oscillator is providing a stable clock
S_SYSCLK
System clock switch status — These bits specify the system clock currently used by the
system.
0000 16 MHz int. RC osc.
0001 reserved
0010 4 MHz crystal osc.
0011 reserved
0100 system PLL
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 system clock is disabled
Table 39. Global Status Register (ME_GS) Field Descriptions (continued)
Field Description
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