ST SPC560P34 - Page 163

RM0046 Mode Entry Module (MC_ME)
Doc ID 16912 Rev 5 163/936
DFLAON Data flash power-down control — This bit specifies the operating mode of the data flash after
entering this mode.
00 reserved
01 Data flash is in power-down mode
10 reserved
11 Data flash is in normal mode
CFLAON Code flash power-down control — This bit specifies the operating mode of the code flash after
entering this mode.
00 reserved
01 Code flash is in power-down mode
10 Code flash is in low-power mode
11 Code flash is in normal mode
PLL0ON
system PLL control
0 system PLL is switched off
1 system PLL is switched on
XOSC0ON
4 MHz crystal oscillator control
0 4 MHz crystal oscillator is switched off
1 4 MHz crystal oscillator is switched on
16 MHz_IRCON
16 MHz internal RC oscillator control
0 16 MHz internal RC oscillator is switched off
1 16 MHz internal RC oscillator is switched on
SYSCLK
System clock switch control — These bits specify the system clock to be used by the system.
0000 16 MHz int. RC osc.
0001 reserved
0010 4 MHz crystal osc.
0011 reserved
0100 system PLL
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 system clock is disabled in TEST mode, reserved in all other modes
Table 46. Mode Configuration Registers (ME_<mode>_MC) Field Descriptions (continued)
Field Description