RM0046 Mode Entry Module (MC_ME)
Doc ID 16912 Rev 5 171/936
If the outputs of the system I/Os need to be forced to a high impedance state upon entering
this mode, the PDO bit of the ME_SAFE_MC register should be set. The input levels remain
unchanged.
TEST Mode
The device enters this mode on the following events:
● from the DRUN mode when the TARGET_MODE bit field of the ME_MCTL register is
written with “0001”
As soon as any of the above events has occurred, a TEST mode transition request is
generated. The mode configuration information for this mode is provided by the
ME_TEST_MC register. Except for the main voltage regulator, all resources of the system
are configurable in this mode. The system clock to the whole system can be stopped by
programming the SYSCLK bit field to “1111”, and in this case, the only way to exit this mode
is via a device reset.
This mode is intended to be used by software
● to execute software test routines
Note: Software must ensure that the code executes from RAM before changing to this mode if the
flashes are configured to be in the low-power or power-down state in this mode.
RUN0…3 Modes
The device enters one of these modes on the following events:
● from the DRUN, SAFE, or another RUN0…3 mode when the TARGET_MODE bit field
of the ME_MCTL register is written with “0100…0111”
● from the HALT0 mode due to an interrupt event
● from the STOP0 mode due to an interrupt or wakeup event
As soon as any of the above events has occurred, a RUN0…3 mode transition request is
generated. The mode configuration information for these modes is provided by the
ME_RUN0…3_MC registers. In these modes, the flashes, all clock sources, and the system
clock configuration can be controlled by software as required.
These modes are intended to be used by software
● to execute application routines
Note: Software must ensure that the code executes from RAM before changing to this mode if the
flashes are configured to be in the low-power or power-down state in this mode.
HALT0 Mode
The device enters this mode on the following events:
● from one of the RUN0…3 modes when the TARGET_MODE bit field of the ME_MCTL
register is written with “1000”.
As soon as any of the above events has occurred, a HALT0 mode transition request is
generated. The mode configuration information for this mode is provided by ME_HALT0_MC
register. This mode is quite configurable, and the ME_HALT0_MC register should be
programmed according to the system needs. The flashes can be put in low-power or power-
down mode as needed. If there is a HALT0 mode request while an interrupt request is
active, the transition to HALT0 is aborted with the resultant mode being the current mode,
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