RM0046 Interrupt Controller (INTC)
Doc ID 16912 Rev 5 233/936
Software vector mode
interrupt_exception_handler:
code to create stack frame, save working register, and save SRR0 and SRR1
lis r3,INTC_IACKR@ha # form adjusted upper half of INTC_IACKR address
lwz r3,INTC_IACKR@l(r3) # load INTC_IACKR, which clears request to
processor
lwz r3,0x0(r3) # load address of ISR from vector table
wrteei 1 # enable processor recognition of interrupts
code to save rest of context required by e500 EABI
mtlr r3 # move INTC_IACKR contents into link register
blrl # branch to ISR; link register updated with epilog
# address
epilog:
code to restore most of context required by e500 EABI
# Popping the LIFO after the restoration of most of the context and the
disabling of processor
# recognition of interrupts eases the calculation of the maximum stack depth
at the cost of
# postponing the servicing of the next interrupt request.
mbar # ensure store to clear flag bit has completed
lis r3,INTC_EOIR@ha # form adjusted upper half of INTC_EOIR address
li r4,0x0 # form 0 to write to INTC_EOIR
wrteei 0 # disable processor recognition of interrupts
stw r4,INTC_EOIR@l(r3) # store to INTC_EOIR, informing INTC to lower
priority
code to restore SRR0 and SRR1, restore working registers, and delete stack
frame
rfi
vector_table_base_address:
address of ISR for interrupt with vector 0
address of ISR for interrupt with vector 1
.
.
.
address of ISR for interrupt with vector 510
address of ISR for interrupt with vector 511
ISRx:
code to service the interrupt event
code to clear flag bit that drives interrupt request to INTC
blr # return to epilog
Hardware vector mode
This interrupt exception handler is useful with processor and system bus implementations
that support a hardware vector. This example assumes that each
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