RM0046 Flash Memory
Doc ID 16912 Rev 5 337/936
The main, shadow, and test address space can be read only in the read state.
The Flash registers are always available for reads. When the module is in power-down
mode, most (but not all) registers are available for reads. The exceptions are documented.
The Flash module enters the read state on reset.
The module is in the read state under two sets of conditions:
● The read state is active when the module is enabled (User mode read).
● The read state is active when MCR[ERS] and MCR[ESUS] are set and MCR[PGM] is
cleared (Erase Suspend).
No Read-While-Modify is available within an individual module, although one module can be
read while the other is being written or otherwise modified.
Flash core reads return 128 bits (1 page = 2 double words).
Register reads return 32 bits (1 word).
Flash core reads are done through the BIU.
Register reads to unmapped register address space return all 0s.
Register writes to unmapped register address space have no effect.
Array reads attempted to invalid locations will result in indeterminate data. Invalid locations
occur when addressing is done to blocks that do not exist in non 2
n
array sizes.
Interlock writes attempted to invalid locations, will result in an interlock occurring, but
attempts to program these blocks will not occur since they are forced to be locked. Erase will
occur to selected and unlocked blocks even if the interlock write is to an invalid location.
Simultaneous read cycles on the code Flash block and read/write cycles on the data Flash
block are possible. However, simultaneous read/write accesses within a single block are not
permitted.
Chip Select, Write Enable, addresses, and data input of registers are not internally latched
and must be kept stable by the CPU for all the read/write access that lasts two clock cycles.
Low-power mode
The Low-power mode turns off most of the DC current sources within the Flash module.
The module (Flash core and registers) is not accessible for read or write operations once it
has entered Low-power mode.
Wake-up time from Low-power mode is faster than wake-up time from Power-down mode.
The user may not read some registers (UMISR0–4, UT1–2 and part of UT0) until the Low-
power mode is exited. Write access is locked on all the registers in Low-power mode.
When exiting from Low-power mode, the Flash module returns to its previous state in all
cases, unless it was in the process of executing an erase high voltage operation at the time
of entering Low-power mode.
If the Flash module is put into Low-power mode during an erase operation, the MCR[ESUS]
bit is set to 1. The user may resume the erase operation when the Flash module exits from
Low-power mode by clearing MCR[ESUS]. MCR[EHV] must be set to resume the erase
operation.
If the Flash module is put in Low-power mode during a program operation, the operation is
completed in all cases. Low-power mode is entered only after the programming ends.
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