Flash Memory RM0046
356/936 Doc ID 16912 Rev 5
25-26
B0_P0_BCFG
Bank0, Port 0 Page Buffer Configuration
This field controls the configuration of the four page buffers in the PFlash controller. The buffers
can be organized as a “pool” of available resources, or with a fixed partition between instruction
and data buffers.
If enabled, when a buffer miss occurs, it is allocated to the least-recently-used buffer within the
group and the just-fetched entry then marked as most-recently-used. If the Flash access is for
the next-sequential line, the buffer is not marked as most-recently-used until the given address
produces a buffer hit.
00 All four buffers are available for any Flash access, that is, there is no partitioning of the buffers
based on the access type.
01 Reserved.
10 The buffers are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches
and buffers 2 and 3 for data accesses.
11 The buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches
and buffer 3 for data accesses.
This field is set to 2b11 by hardware reset.
27
B0_P0_DPFE
Bank0, Port 0 Data Prefetch Enable
This field enables or disables prefetching initiated by a data read access. This field is cleared by
hardware reset.
0 No prefetching is triggered by a data read access.
1 If page buffers are enabled (B0_P0_BFE = 1), prefetching is triggered by any data read access.
28
B0_P0_IPFE
Bank0, Port 0 Instruction Prefetch Enable
This field enables or disables prefetching initiated by an instruction fetch read access. This field
is set by hardware reset.
0 No prefetching is triggered by an instruction fetch read access.
1 If page buffers are enabled (B0_P0_BFE = 1), prefetching is triggered by any instruction fetch
read access.
29-30
B0_P0_PFLM
Bank0, Port 0 Prefetch Limit
This field controls the prefetch algorithm used by the PFlash controller. This field defines the
prefetch behavior. In all situations when enabled, only a single prefetch is initiated on each buffer
miss or hit. This field is set to 2b10 by hardware reset.
00 No prefetching is performed.
01 The referenced line is prefetched on a buffer miss, that is, prefetch on miss.
1x The referenced line is prefetched on a buffer miss, or the next sequential page is prefetched
on a buffer hit (if not already present), that is, prefetch on miss or hit.
31
B0_P0_BFE
Bank0, Port 0 Buffer Enable
This bit enables or disables page buffer read hits. It is also used to invalidate the buffers. This bit
is set by hardware reset.
0 The page buffers are disabled from satisfying read requests, and all buffer valid bits are cleared.
1 The page buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when
the buffers are successfully filled.
Table 156. PFCR0 field descriptions (continued)
Field Description
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