Flash Memory RM0046
358/936 Doc ID 16912 Rev 5
10-14
BK1_RWSC
Bank1 Read Wait State Control
This field controls the number of wait states to be added to the Flash array access time for reads.
This field must be set to a value corresponding to the operating frequency of the PFlash and the
actual read access time of the PFlash. Higher operating frequencies require non-zero settings for
this field for proper Flash operation.
0 MHz, < 23 MHz APC = RWSC = 0.
23 MHz, < 45 MHz APC = RWSC = 1.
45 MHz, < 68 MHz APC = RWSC = 2.
68 MHz, < 90 MHz APC = RWSC = 3.
This field is set to 0b00010 by hardware reset.
00000 No additional wait states are added.
00001 1 additional wait state is added.
00010 2 additional wait states are added.
...
111111 31 additional wait states are added.
15-16,24
BK1_RWWC
Bank1 Read-While-Write Control
This 3-bit field defines the controller response to Flash reads while the array is busy with a program
(write) or erase operation.
0xx Terminate any attempted read while write/erase with an error response.
100 Generate a bus stall for a read while write/erase, enable the operation abort and the abort
notification interrupt.
101 Generate a bus stall for a read while write/erase, enable the operation abort, disable the abort
notification interrupt.
110 Generate a bus stall for a read while write/erase, enable the stall notification interrupt, disable
the abort + abort notification interrupt.
111 Generate a bus stall for a read while write/erase, disable the stall notification interrupt, disable
the abort + abort notification interrupt.
This field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the
abort and notification interrupts.
17-22 Reserved, should be cleared.
23
B1_P1_BFE
Bank1, Port 1 Buffer Enable
This bit enables or disables read hits from the 128-bit holding register. It is also used to invalidate the
contents of the holding register. This bit is set by hardware reset, enabling the use of the holding
register.
0 The holding register is disabled from satisfying read requests.
1 The holding register is enabled to satisfy read requests on hits.
25-30 Reserved, should be cleared.
Table 157. PFCR1 field descriptions (continued)
Field Description
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