Enhanced Direct Memory Access (eDMA) RM0046
418/936 Doc ID 16912 Rev 5
to match the size of the transfer; one byte for the source and four bytes for the destination.
The final source and destination addresses are adjusted to return to their beginning values.
TCD.CITER = TCD.BITER = 1
TCD.NBYTES = 16
TCD.SADDR = 0x1000
TCD.SOFF = 1
TCD.SSIZE = 0
TCD.SLAST = –16
TCD.DADDR = 0x2000
TCD.DOFF = 4
TCD.DSIZE = 2
TCD.DLAST_SGA= –16
TCD.INT_MAJ = 1
TCD.START = 1 (Initialize all other fields before writing to this bit)
All other TCD fields = 0
This generates the following sequence of events:
1. Slave write to the TCD.START bit requests channel service.
2. The channel is selected by arbitration for servicing.
3. eDMA engine writes: TCD.DONE = 0, TCD.START = 0, TCD.ACTIVE = 1.
4. eDMA engine reads: channel TCD data from local memory to internal register file.
5. The source to destination transfers are executed as follows:
a) read_byte (0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003)
b) write_word (0x2000) first iteration of the minor loop
c) read_byte (0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007)
d) write_word (0x2004) second iteration of the minor loop
e) read_byte (0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b)
f) write_word (0x2008) third iteration of the minor loop
g) read_byte (0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f)
h) write_word (0x200c) last iteration of the minor loop major loop complete
6. eDMA engine writes: TCD.SADDR = 0x1000, TCD.DADDR = 0x2000,
TCD.CITER = 1 (TCD.BITER).
7. eDMA engine writes: TCD.ACTIVE = 0, TCD.DONE = 1, EDMA_IRQRn =1.
8. The channel retires.
The eDMA goes idle or services the next channel.
Multiple requests
The next example is the same as previous with the exception of transferring 32 bytes via two
hardware requests. The only fields that change are the major loop iteration count and the
final address offsets. The eDMA is programmed for two iterations of the major loop
transferring 16 bytes per iteration. After the channel’s hardware requests are enabled in the
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