Deserial Serial Peripheral Interface (DSPI) RM0046
458/936 Doc ID 16912 Rev 5
DSPI POP RX FIFO Register (DSPIx_POPR)
The DSPIx_POPR allows you to read the RX FIFO. Refer to Section , “Receive First In First
Out (RX FIFO) buffering mechanism for a description of the RX FIFO operations. Eight or
16-bit read accesses to the DSPIx_POPR fetch the RX FIFO data, and update the counter
and pointer.
Note: Reading the RX FIFO field fetches data from the RX FIFO. Once the RX FIFO is read, the
read data pointer is moved to the next entry in the RX FIFO. Therefore, read DSPIx_POPR
only when you need the data. For compatibility, configure the TLB (MMU table) entry for
DSPIx_POPR as guarded.
4
EOQ
End of queue
Provides a means for host software to signal to the DSPI that the current SPI transfer is the last
in a queue. At the end of the transfer the EOQF bit in the DSPIx_SR is set.
0 The SPI data is not the last data to transfer.
1 The SPI data is the last data to transfer.
Use in SPI master mode only.
5
CTCNT
Clear SPI_TCNT
Provides a means for host software to clear the SPI transfer counter. The CTCNT bit clears the
SPI_TCNT field in the DSPIx_TCR. The SPI_TCNT field is cleared before transmission of the
current SPI frame begins.
0 Do not clear SPI_TCNT field in the DSPIx_TCR.
1 Clear SPI_TCNT field in the DSPIx_TCR.
Use in SPI master mode only.
6–7 Reserved
10–15
PCSx
Peripheral chip select x
Selects which CS
x signals are asserted for the transfer.
0 Negate the CS
x signal.
1 Assert the CSx signal.
Use in SPI master mode only.
16–31
TXDATA
[0:15]
Transmit data
Holds SPI data for transfer according to the associated SPI command.
Use TXDATA in master and slave modes.
Table 217. DSPIx_PUSHR field descriptions (continued)
Field Description
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