eTimer RM0046
724/936 Doc ID 16912 Rev 5
CPT2MODE
Capture 2 Mode Control
These bits control the operation of the CAPT2 register as well as the operation of the ICF2 flag by
defining which input edges cause a capture event. The input source is the secondary count source.
00 Disabled.
01 Capture falling edges.
10 Capture rising edges.
11 Capture any edge.
CPT1MODE
Capture 1 Mode Control
These bits control the operation of the CAPT1 register as well as the operation of the ICF1 flag by
defining which input edges cause a capture event. The input source is the secondary count source.
00 Disabled.
01 Capture falling edges.
10 Capture rising edges.
11 Capture any edge.
CFWM
Capture FIFO Water Mark
This field represents the water mark level for the CAPT1 and CAPT2 FIFOs. The capture flags,
ICF1 and ICF2, are not set until the word count of the corresponding FIFO is greater than this
water mark level.
ONESHOT
One-Shot Capture Mode
This bit selects between free-running and one-shot mode for the input capture circuitry.
If both capture circuits are enabled, then capture circuit 1 is armed first after the ARM bit is set.
Once a capture occurs, capture circuit 1 is disarmed and capture circuit 2 is armed. After capture
circuit 2 performs a capture, it is disarmed and the ARM bit is cleared. No further captures will be
performed until the ARM bit is set again.
If only one of the capture circuits is enabled, then a single capture will occur on the enabled
capture circuit and the ARM bit is then cleared.
If both capture circuits are enabled, then capture circuit 1 is armed first after the ARM bit is set.
Once a capture occurs, capture circuit 1 is disarmed and capture circuit 2 is armed. After capture
circuit 2 performs a capture, it is disarmed and capture circuit 1 is re-armed. The process
continues indefinitely.
If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled
capture circuit.
0 Free-running mode is selected
1 One-shot mode is selected.
ARM
Arm Capture
Setting this bit high starts the input capture process. This bit can be cleared at any time to disable
input capture operation. This bit is self cleared when in one-shot mode and the enabled capture
circuit(s) has had a capture event(s).
0 Input capture operation is disabled.
1 Input capture operation as specified by the CPT1MODE and CPT2MODE bits is enabled.
Table 380. CCCTRL field descriptions (continued)
Field Description
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