Wakeup Unit (WKPU) RM0046
780/936 Doc ID 16912 Rev 5
NMI management
The NMI can be enabled or disabled using the single NCR register laid out to contain all
configuration bits for an NMI in a single byte (see Figure 454). The pad defined as an NMI
can be configured by the user to recognize interrupts with an active rising edge, an active
falling edge or both edges being active. A setting of having both edge events disabled
results in no interrupt being detected and should not be configured.
The active NMI edge is controlled by the user through the configuration of the NREE and
NFEE bits.
Note: After reset, NREE and NFEE are set to 0, therefore the NMI functionality is disabled after
reset and must be enabled explicitly by software.
Once the pad’s NMI functionality has been enabled, the pad cannot be reconfigured in the
IOMUX to override or disable the NMI.
The NMI destination interrupt is controlled by the user through the configuration of the
NDSS bits. See Table 416 for details.
An NMI supports a status flag and an overrun flag, which are located in the NSR register
(see Figure 453). This register is a clear-by-write-1 register type, preventing inadvertent
overwriting of other flags in the same register. The status flag is set whenever an NMI event
is detected. The overrun flag is set whenever an NMI event is detected and the status flag is
set (that is, has not yet been cleared).
Note: The overrun flag is cleared by writing a 1 to the appropriate overrun bit in the NSR register.
If the status bit is cleared and the overrun bit is still set, the pending interrupt will not be
cleared.
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