ST SPC560P34 - Page 378

Flash Memory RM0046
378/936 Doc ID 16912 Rev 5
data4 = UMISR4; /* Read UMISR4 content*/
UT0 = 0x80000034; /* Reset AIE in UT0: Operation End */
UT0 = 0x00000000; /* Reset UTE, MRE, MRV, AIS in UT0: Deselect Op. */
ECC logic check
ECC logic can be checked by forcing the input of ECC logic: The 64 bits of data and the 8
bits of ECC syndrome can be individually forced and they will drive simultaneously at the
same value the ECC logic of the whole page (2 double words).
The results of the ECC Logic Check can be verified by reading the MISR value.
The ECC Logic Check operation consists of the following sequence of events:
1. Set UT0[UTE] by writing the related password in UT0.
2. Write the double word input value to UT1[DAI31–0] and UT2[DAI[63–32].
3. Write the Syndrome Input value to UT0[DSI7–0].
4. Select the ECC Logic Check: write a logic 1 to the UT0[EIE] bit.
5. Write a logic 1 to the UT0[AIE] bit to start the ECC Logic Check.
6. Wait until the UT0[AID] bit goes high.
7. Compare the contents of the UMISR0–4 registers with the expected results.
8. Write a logic 0 to the UT0[AIE] bit.
Notice that when UT0[AID] = 0, the UMISR0–4 and UT1–2 registers and the UT0[MRE],
UT0[MRV], UT0[EIE], UT0[AIS], and UT0[DSI7–0] bits are not accessible. Reads return
indeterminate data; writes have no effect.
Example 7ECC logic check
UT0 = 0xF9F99999; /* Set UTE in UT0: Enable User Test */
UT1 = 0x55555555; /* Set DAI31-0 in UT1: Even Word Input Data */
UT2 = 0xAAAAAAAA; /* Set DAI63-32 in UT2: Odd Word Input Data */
UT0 = 0x80FF0000; /* Set DSI7-0 in UT0: Syndrome Input Data */
UT0 = 0x80FF0008; /* Set EIE in UT0: Select ECC Logic Check */
UT0 = 0x80FF000A; /* Set AIE in UT0: Operation Start */
do /* Loop to wait for AID=1 */
{ tmp = UT0; /* Read UT0 */
} while ( !(tmp & 0x00000001) );
data0 = UMISR0; /* Read UMISR0 content (expected 0x55555555) */
data1 = UMISR1; /* Read UMISR1 content (expected 0xAAAAAAAA) */
data2 = UMISR2; /* Read UMISR2 content (expected 0x55555555) */
data3 = UMISR3; /* Read UMISR3 content (expected 0xAAAAAAAA) */
data4 = UMISR4; /* Read UMISR4 content (expected 0x00FF00FF) */
UT0 = 0x00000000; /* Reset UTE, AIE and EIE in
UT0: Operation End */
Error Correction Code (ECC)
The Flash macrocell provides a method to improve the reliability of the data stored in Flash:
the usage of an Error Correction Code. The word size is fixed at 64 bits.
Each double word of 64 bits has an associated 8 ECC bits that are programmed in such a
way to guarantee a Single Error Correction and a Double Error Detection (SEC-DED).
ECC circuitry provides correction of single bit faults and is used to achieve automotive
reliability targets. Some units will experience single bit corrections throughout the life of the
product with no impact on product reliability.