RM0046 Flash Memory
Doc ID 16912 Rev 5 377/936
Since Margin reads are done at voltages that differ than the normal read voltage, the lifetime
expectancy of the Flash macrocell is impacted by the execution of Margin reads.
Repeated Margin reads will result in degradation of the Flash array, and will shorten the
expected lifetime experienced at normal read levels.
For these reasons, Margin reads are allowed only at the factory. Margin reads are forbidden
for use by user applications.
In any case the charge losses detected through the Margin mode cannot be considered
failures of the device and no failure analysis will be opened on them.
The Margin Read Setup operation consists of the following sequence of events:
1. Set UTE in UT0 by writing the related password in UT0.
2. Select the block(s) to be checked by writing 1s to the LMS register.
Note that Lock and Select are independent. If a block is selected and locked, no Array
Integrity Check will occur.
3. Set UT0[AIS] bit for a sequential addressing only.
4. Change the value in the UT0[MRE] bit from 0 to 1.
5. Select the Margin level: UT0[MRV] = 0 for 0s margin, UT0[MRV] = 1 for 1s margin.
6. Write a logic 1 to the UT0[AIE] bit to start the Margin Read.
7. Wait until the UT0[AID] bit goes high.
8. Compare UMISR[0:4] content with the expected result.
9. Write a logic 0 to the UT0[AIE], UT0[MRE] and UT0[MRV] bits.
10. If more blocks are to be checked, return to step 2.
It is mandatory to leave UT0[AIS] at 1 and use the linear address sequence (that also takes
less time).
During the execution of the Margin Mode operation it is forbidden to modify the content of
Block Select (LMS) and Lock (LML, SLL) registers, otherwise the MISR value can vary in an
unpredictable way.
The read accesses will be done with the addition of a proper number of wait states to
guarantee the correctness of the result.
While UT0[AID] is low and UT0[AIE] is high, the user may clear AIE, resulting in a Array
Integrity Check termination.
UT0[AID] must be checked to know when the terminating command has completed.
Example 6Margin Read Check versus 1s
UT0 = 0xF9F99999; /* Set UTE in UT0: Enable User Test */
LMS = 0x00000006; /* Set LSL2-1 in LMS: Select Sectors */
UT0 = 0x80000004; /* Set AIS in UT0: Select Operation */
UT0 = 0x80000024; /* Set MRE in UT0: Select Operation */
UT0 = 0x80000034; /* Set MRV in UT0: Select Margin versus 1’s */
UT0 = 0x80000036; /* Set AIE in UT0: Operation Start */
do /* Loop to wait for AID=1 */
{ tmp = UT0; /* Read UT0 */
} while ( !(tmp & 0x00000001) );
data0 = UMISR0; /* Read UMISR0 content*/
data1 = UMISR1; /* Read UMISR1 content*/
data2 = UMISR2; /* Read UMISR2 content*/
data3 = UMISR3; /* Read UMISR3 content*/
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