Flash Memory RM0046
376/936 Doc ID 16912 Rev 5
The 128-bit data and the 16-bit ECC data are sampled before the eventual ECC correction,
while the single and double error flags are sampled after the ECC evaluation.
Only data from existing and unlocked locations are captured by the MISR.
The MISR can be seeded to any value by writing the UMISR0–4 registers.
The Array Integrity Self Check consists of the following sequence of events:
1. Set UT0[UTE] by writing the related password in UT0.
2. Select the block(s) to be checked by writing 1s to the LMS register.
Note that Lock and Select are independent. If a block is selected and locked, no Array
Integrity Check will occur.
3. Set eventually UT0[AIS] bit for a sequential addressing only.
4. Write a logic 1 to the UT0[AIE] bit to start the Array Integrity Check.
5. Wait until the UT0[AID] bit is set.
6. Compare the contents of the UMISR0–4 registers with the expected results.
7. Write a logic 0 to the UT0[AIE] bit.
8. If more blocks are to be checked, return to step 2.
It is recommended to leave UT0[AIS] at 0 and use the proprietary address sequence that
checks the read path more fully, although this sequence takes more time.
Note: During the execution of the Array Integrity Check operation it is forbidden to modify the
content of Block Select (LMS) and Lock (LML, SLL) registers, otherwise the MISR value can
vary in an unpredictable way.
While UT0[AID] is low and UT0[AIE] is high, the user may clear UT0[AIE], resulting in an
Array Integrity Check termination.
UT0[AID] must be checked to know when the terminating command has completed.
Example 5Array Integrity Check of sectors B0F1 and B0F2
UT0 = 0xF9F99999; /* Set UTE in UT0: Enable User Test */
LMS = 0x00000006; /* Set LSL2-1 in LMS: Select Sectors */
UT0 = 0x80000002; /* Set AIE in UT0: Operation Start */
do /* Loop to wait for AID=1 */
{ tmp = UT0; /* Read UT0 */
} while ( !(tmp & 0x00000001) );
data0 = UMISR0; /* Read UMISR0 content*/
data1 = UMISR1; /* Read UMISR1 content*/
data2 = UMISR2; /* Read UMISR2 content*/
data3 = UMISR3; /* Read UMISR3 content*/
data4 = UMISR4; /* Read UMISR4 content*/
UT0 = 0x00000000; /* Reset UTE and AIE in UT0:
Operation End */
Margin read
The Margin read procedure (either Margin 0 or Margin 1) can be run on unlocked blocks in
order to unbalance the Sense Amplifiers with respect to standard read conditions so that all
the read accesses reduce the margin vs. 0 (UT0[MRV] = 0) or vs. 1 (UT0[MRV] = 1). Locked
sectors are ignored by MISR calculation and ECC flagging.
The results of the margin reads can be checked by comparing the checksum value in
UMISR[0:4].
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