RM0046 Deserial Serial Peripheral Interface (DSPI)
Doc ID 16912 Rev 5 445/936
5
MTFE
Modified timing format enable
Enables a modified transfer format to be used. Refer to Section , “Modified SPI transfer format
(MTFE = 1, CPHA = 1) for more information.
0 Modified SPI transfer format disabled
1 Modified SPI transfer format enabled
6
PCSSE
Peripheral chip select strobe enable
Enables the CS5_
x to operate as a CS strobe output signal.
Refer to Section , “Peripheral Chip Select strobe enable (CS5_x) for more information.
0CS5_
x is used as the Peripheral chip select 5 signal.
1CS5_
x is used as an active-low CS strobe signal.
7
ROOE
Receive FIFO overflow overwrite enable
Enables an RX FIFO overflow condition to ignore the incoming serial data or to overwrite existing
data. If the RX FIFO is full and new data is received, the data from the transfer that generated the
overflow is ignored or put in the shift register.
If the ROOE bit is set, the incoming data is put in the shift register. If the ROOE bit is cleared, the
incoming data is ignored. Refer to Section , “Receive FIFO overflow interrupt request (RFOF) for
more information.
0 Incoming data is ignored.
1 Incoming data is put in the shift register.
8–9 Reserved, but implemented. These bits are writable, but have no effect.
10–15
PCSISn
Peripheral chip select inactive state
Determines the inactive state of the CS0_
x signal. CS0_x must be configured as inactive high for
slave mode operation.
0 The inactive state of CS0_
x is low.
1 The inactive state of CS0_x is high.
PCSIS7 and PSCIS6 are implemented only on DSPI_0.
16 Reserved
17
MDIS
Module disable
Allows the clock to stop to the non-memory mapped logic in the DSPI, effectively putting the DSPI
in a software controlled power-saving state. Refer to Section 20.8.8, “Power saving features for
more information.” The reset value of the MDIS bit is parameterized, with a default reset value of 0.
0 Enable DSPI clocks.
1 Allow external logic to disable DSPI clocks.
18
DIS_TXF
Disable transmit FIFO
Enables and disables the TX FIFO. When the TX FIFO is disabled, the transmit part of the DSPI
operates as a simplified double-buffered SPI. Refer to Section , “FIFO disable operation for details.
0TX FIFO enabled
1TX FIFO disabled
19
DIS_RXF
Disable receive FIFO
Enables and disables the RX FIFO. When the RX FIFO is disabled, the receive part of the DSPI
operates as a simplified double-buffered SPI. Refer to Section , “FIFO disable operation for details.
0 RX FIFO enabled
1 RX FIFO disabled
Table 206. DSPIx_MCR field descriptions (continued)
Field Description
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