ST SPC560P34 - Page 446

Deserial Serial Peripheral Interface (DSPI) RM0046
446/936 Doc ID 16912 Rev 5
DSPI Transfer Count Register (DSPIx_TCR)
The DSPIx_TCR contains a counter that indicates the number of SPI transfers made. The
transfer counter is intended to assist in queue management. The user must not write to the
DSPIx_TCR while the DSPI is running.
20
CLR_TXF
Clear TX FIFO
Flushes the TX FIFO. Write a 1 to the CLR_TXF bit to clear the TX FIFO counter. The CLR_TXF
bit is always read as 0.
0 Do not clear the TX FIFO counter.
1 Clear the TX FIFO counter.
21
CLR_RXF
Clear RX FIFO
Flushes the RX FIFO. Write a 1 to the CLR_RXF bit to clear the RX counter. The CLR_RXF bit is
always read as 0.
0 Do not clear the RX FIFO counter.
1 Clear the RX FIFO counter.
22–23
SMPL_PT
[0:1]
Sample point
Allows the host software to select when the DSPI master samples SIN in modified transfer format.
Figure 222 shows where the master can sample the SIN pin. The following table lists the delayed
sample points.
24–30 Reserved
31
HALT
Halt
Provides a mechanism for software to start and stop DSPI transfers. Refer to Section 20.8.2, “Start
and stop of DSPI transfers for details on the operation of this bit.
0 Start transfers.
1 Stop transfers.
Table 206. DSPIx_MCR field descriptions (continued)
Field Description
SMPL_PT
Number of system clock cycles between
odd-numbered edge of SCK_x and sampling of SIN_x
00 0
01 1
10 2
11 Invalid value