Deserial Serial Peripheral Interface (DSPI) RM0046
464/936 Doc ID 16912 Rev 5
The SPI configuration supports two module-specific modes; master mode and slave mode.
The FIFO operations are similar for the master mode and slave mode. The main difference
is that in master mode the DSPI initiates and controls the transfer according to the fields in
the SPI command field of the TX FIFO entry. In slave mode the DSPI only responds to
transfers initiated by a bus master external to the DSPI and the SPI command field of the TX
FIFO entry is ignored.
SPI master mode
In SPI master mode the DSPI initiates the serial transfers by controlling the serial
communications clock (SCK_x) and the peripheral chip select (CS
x) signals. The SPI
command field in the executing TX FIFO entry determines which CTARs set the transfer
attributes and which CS
x signals to assert. The command field also contains various bits
that help with queue management and transfer protocol. The data field in the executing TX
FIFO entry is loaded into the shift register and shifted out on the serial out (SOUT_x) pin. In
SPI master mode, each SPI frame to be transmitted has a command associated with it
allowing for transfer attribute control on a frame by frame basis.
Refer to Section , “DSPI PUSH TX FIFO Register (DSPIx_PUSHR) for details on the SPI
command fields.
SPI slave mode
In SPI slave mode the DSPI responds to transfers initiated by an SPI bus master. The DSPI
does not initiate transfers. Certain transfer attributes such as clock polarity, clock phase and
frame size must be set for successful communication with an SPI master. The SPI slave
mode transfer attributes are set in the DSPIx_CTAR0.
FIFO disable operation
The FIFO disable mechanisms allow SPI transfers without using the TX FIFO or RX FIFO.
The DSPI operates as a double-buffered simplified SPI when the FIFOs are disabled. The
TX and RX FIFOs are disabled separately. The TX FIFO is disabled by writing a 1 to the
DIS_TXF bit in the DSPIx_MCR. The RX FIFO is disabled by writing a 1 to the DIS_RXF bit
in the DSPIx_MCR.
The FIFO disable mechanisms are transparent to the user and to host software; transmit
data and commands are written to the DSPIx_PUSHR and received data is read from the
DSPIx_POPR. When the TX FIFO is disabled, the TFFF, TFUF, and TXCTR fields in
DSPIx_SR behave as if there is a one-entry FIFO but the contents of the DSPIx_TXFRs and
TXNXTPTR are undefined. When the RX FIFO is disabled, the RFDF, RFOF, and RXCTR
fields in the DSPIx_SR behave as if there is a one-entry FIFO but the contents of the
DSPIx_RXFRs and POPNXTPTR are undefined.
Disable the TX and RX FIFOs only if the FIFO must be disabled as a requirement of the
application's operating mode. A FIFO must be disabled before it is accessed. Failure to
disable a FIFO prior to a first FIFO access is not supported, and can result in incorrect
results.
Transmit First In First Out (TX FIFO) buffering mechanism
The TX FIFO functions as a buffer of SPI data and SPI commands for transmission. The TX
FIFO holds five entries, each consisting of a command field and a data field. SPI commands
and data are added to the TX FIFO by writing to the DSPI push TX FIFO register
(DSPIx_PUSHR). For more information on DSPIx_PUSHR refer to Section , “DSPI PUSH
TX FIFO Register (DSPIx_PUSHR).” TX FIFO entries can only be removed from the TX
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