RM0046 Deserial Serial Peripheral Interface (DSPI)
Doc ID 16912 Rev 5 465/936
FIFO by being shifted out or by flushing the TX FIFO.
The TX FIFO counter field (TXCTR) in the DSPI status register (DSPIx_SR) indicates the
number of valid entries in the TX FIFO. The TXCTR is updated every time the DSPI
_PUSHR is written or SPI data is transferred into the shift register from the TX FIFO.
Refer to Section , “DSPI Status Register (DSPIx_SR) for more information on DSPIx_SR.
The TXNXTPTR field indicates which TX FIFO entry is transmitted during the next transfer.
The TXNXTPTR contains the positive offset from DSPIx_TXFR0 in number of 32-bit
registers. For example, TXNXTPTR equal to two means that the DSPIx_TXFR2 contains the
SPI data and command for the next transfer. The TXNXTPTR field is incremented every
time SPI data is transferred from the TX FIFO to the shift register.
Filling the TX FIFO
Host software or the eDMA controller can add (push) entries to the TX FIFO by writing to the
DSPIx_PUSHR. When the TX FIFO is not full, the TX FIFO fill flag (TFFF) in the DSPIx_SR
is set. The TFFF bit is cleared when the TX FIFO is full and the eDMA controller indicates
that a write to DSPIx_PUSHR is complete or alternatively by host software writing a 1 to the
TFFF in the DSPIx_SR. The TFFF can generate a DMA request or an interrupt request.
Refer to Section , “Transmit FIFO fill interrupt or DMA request (TFFF) for details.
The DSPI ignores attempts to push data to a full TX FIFO; that is, the state of the TX FIFO is
unchanged. No error condition is indicated.
Draining the TX FIFO
The TX FIFO entries are removed (drained) by shifting SPI data out through the shift
register. Entries are transferred from the TX FIFO to the shift register and shifted out as long
as there are valid entries in the TX FIFO. Every time an entry is transferred from the TX
FIFO to the shift register, the TX FIFO counter is decremented by one. At the end of a
transfer, the TCF bit in the DSPIx_SR is set to indicate the completion of a transfer. The TX
FIFO is flushed by writing a 1 to the CLR_TXF bit in DSPIx_MCR.
If an external SPI bus master initiates a transfer with a DSPI slave while the slave’s DSPI TX
FIFO is empty, the transmit FIFO underflow flag (TFUF) in the slave’s DSPIx_SR is set.
Refer to Section , “Transmit FIFO underflow interrupt request (TFUF) for details.
Receive First In First Out (RX FIFO) buffering mechanism
The RX FIFO functions as a buffer for data received on the SIN pin. The RX FIFO holds five
received SPI data frames. SPI data is added to the RX FIFO at the completion of a transfer
when the received data in the shift register is transferred into the RX FIFO. SPI data is
removed (popped) from the RX FIFO by reading the DSPIx_POPR register. RX FIFO entries
can only be removed from the RX FIFO by reading the DSPIx_POPR or by flushing the RX
FIFO.
Refer to Section , “DSPI POP RX FIFO Register (DSPIx_POPR) for more information on the
DSPIx_POPR.
The RX FIFO counter field (RXCTR) in the DSPI status register (DSPIx_SR) indicates the
number of valid entries in the RX FIFO. The RXCTR is updated every time the DSPI _POPR
is read or SPI data is copied from the shift register to the RX FIFO.
The POPNXTPTR field in the DSPIx_SR points to the RX FIFO entry that is returned when
the DSPIx_POPR is read. The POPNXTPTR contains the positive, 32-bit word offset from
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