ST SPC560P34 - Page 930

Document revision history RM0046
930/936 Doc ID 16912 Rev 5
11-May-2011
3
cont’d
“Deserial Serial Peripheral Interface (DSPI)” chapter
In the “DSPI memory map” table, removed access and reset columns.
In the “DSPI block diagram” figure, replace arrow labels from “1” to “3”.
In the DSPIx_MCR.CONT_SCKE filed description, added a note.
In the “Continuous Serial Communications clock” section, added a note.
In the “Continuous Selection Format” section, added a note.
“LIN Controller (LINFlex)” chapter
In the “IFER field descriptions” table, switched “activated” and “deactivated” in order to
match with “IFER[FACT] configuration” table.
In the “UART mode” section, in the “9-bit frames” subsection, changed “sum of the 7 data
bits” to “sum of the 8 data bits”.
“FLexCAN” chapter
In the “Module Configuration Register (MCR)” section, changed DOZE field to reserved
bit
In the “Freeze mode”, replaced “(Disable, Doze, Stop)” with “(Halt, Stop)” in first
paragraph
In the “Module Configuration Register (MCR)” figure, changed reset value for field
MAXMB[5:0] from 000000 to 001111
In the “Freeze mode” section: Deleted “(Halt, Stop)” in first paragraph
In the “FlexCAN module memory map” table, removed access and reset columns.
In the “Message Buffer lock mechanism” section, updated a footnote
“Analog-to-Digital Converter (ADC)” chapter:
In the “Conversion timing registers CTR” section, removed footnote.
in the Device-specific features section, removed "internal standard channels" from
"Sampling and conversion time register" bullet
In the “Mask registers” section changed the number of channel from 96 to 16.
In the “Channel Data Register (CDR)” section changed the number of channel from 95 to
15
“FlexPWM” chapter
“Capture Value 0 Cycle register (CVAL0CYC)” and “Capture Value 1 Cycle register
(CVAL1CYC)” use only bits [13:15] instead of bits[12:15]
Replaced instances of WAIT mode with WAIT/HALT mode
Device-specific changes:
DMAEN field descriptions: Removed reference to bits CAxDE and CBxDE from FAND
field description
“Functional Safety” chapter:
In the “ Register protection memory map” table, removed access and reset columns.
In the “SWT memory map” table, removed access and reset columns per new agreement.
In the “SWT Control Register (SWT_CR)” table, changed the reset value from
0x4000_011B to 0xFF00_011B.
In the “SWT memory map” table, inserted the SWT_1 offset value
Table 476. Revision history (continued)
Date Revision Changes