ST SPC560P34 - Page 922

Registers Under Protection RM0046
922/936 Doc ID 16912 Rev 5
FlexPWM SUB3_OCTRL 16 0x0108 16-bit
FlexPWM SUB3_INTEN 16 0x010C 16-bit
FlexPWM SUB3_DMAEN 16 0x010E 16-bit
FlexPWM SUB3_TCTRL 16 0x0110 16-bit
FlexPWM SUB3_DISMAP 16 0x0112 16-bit
FlexPWM SUB3_DTCNT0 16 0x0114 16-bit
FlexPWM SUB3_DTCNT1 16 0x0116 16-bit
FlexPWM MASK 16 0x0142 16-bit
FlexPWM SWCOUT 16 0x0144 16-bit
FlexPWM DTSRCSEL 16 0x0146 16-bit
FlexPWM MCTRL 16 0x0148 16-bit
FlexPWM FCTRL 16 0x014C 16-bit
DSPI 0—Base address: 0xFFF9_0000
11 registers to protect
DSPI 0 DSPI_MCR 32 0x0000 32-bit
DSPI 0 DSPI_TCR 32 0x0008 32-bit
DSPI 0 DSPI_CTAR0 32 0x000C 32-bit
DSPI 0 DSPI_CTAR1 32 0x0010 32-bit
DSPI 0 DSPI_CTAR2 32 0x0014 32-bit
DSPI 0 DSPI_CTAR3 32 0x0018 32-bit
DSPI 0 DSPI_CTAR4 32 0x001C 32-bit
DSPI 0 DSPI_CTAR5 32 0x0020 32-bit
DSPI 0 DSPI_CTAR6 32 0x0024 32-bit
DSPI 0 DSPI_CTAR7 32 0x0028 32-bit
DSPI 0 DSPI_RSER 32 0x0030 32-bit
DSPI 1—Base address: 0xFFF9_4000
11 registers to protect
DSPI 1 DSPI_MCR 32 0x0000 32-bit
DSPI 1 DSPI_TCR 32 0x0008 32-bit
DSPI 1 DSPI_CTAR0 32 0x000C 32-bit
DSPI 1 DSPI_CTAR1 32 0x0010 32-bit
DSPI 1 DSPI_CTAR2 32 0x0014 32-bit
DSPI 1 DSPI_CTAR3 32 0x0018 32-bit
Table 475. Registers under protection (continued)
Module Register Register size (bits) Register offset Protected bitfields