ST SPC560P34 - Page 927

RM0046 Document revision history
Doc ID 16912 Rev 5 927/936
30-Jun-2010 2
23, Analog-to-Digital Converter (ADC)
ADC digital registers: Removed Channel Pending Registers (CEOCFR[x]) and Decode
Signals Delay Register (DSDR)
Section 23.3.3, ADC sampling and conversion timing: Corrected instances of bitfield
name INPSAMPLE to INPSAMP
Section 23.3.7, Interrupts: Removed content concerning register CEOCFR
24, “Cross Triggering Unit (CTU)
Section 24.4.1, “ADC commands list: Minor editorial change
Section 24.8.13, “FIFO threshold register (FTH): Amended and corrected register name
25, “FlexPWM
Editorial and formatting changes
“Capture Value 0 Cycle register (CVAL0CYC)” and “Capture Value 1 Cycle register
(CVAL1CYC)” use only bits [13:15] instead of bits[12:15]
Replaced instances of WAIT mode with WAIT/HALT mode
Changed FSTS register reset value from 0x0000 to 0x0303
26, “eTimer: Unchanged from previous revision
27, “Functional Safety: Unchanged from previous revision
28, “Fault Collection Unit (FCU)
Section , “Test mode: Removed sentence referencing software-triggered faults not being
supported by the FCU_FFGR
Register summary:
– In FCU_FFR, changed field SRF1 to read-only with value 0
– In FCU_FFFR, changed field FRSRF1 to read-only with value 0
Section , “Fault Flag Register (FCU_FFR): Removed sentence referencing clearing the
software fault flag SRF1; changed field SRF1 to read-only with value 0
Hardware/software fault description: Marked SRF1 as “Not used”
Section , “Frozen Fault Flag Register (FCU_FFFR): Changed field FRSRF1 to read-only
with value 0
FCU_FER field descriptions: Added note that field ESF1 not implemented
FCU_TER field descriptions: Added note that field TESF1 not implemented
Section , “Microcontroller State Register (FCU_MCSR): Updated bit values
Section , “Frozen MC State Register (FCU_FMCSR): Updated bit values
29, “Wakeup Unit (WKPU): Unchanged from previous revision
30, “Periodic Interrupt Timer (PIT)
Section 30.3, “Memory map and registers description: Minor formatting changes
throughout
Section , “PIT Module Control Register (PITMCR): Added field MDIS (bit 30)
31, “System Timer Module (STM): Unchanged from previous revision
32, “Cyclic Redundancy Check (CRC)
CRC computation flow: Replaced CRC_CNTX_NUM with "n"
Improved readability of DMA-CRC Transmission Sequence and of DMA-CRC Reception
Sequence
Table 476. Revision history (continued)
Date Revision Changes