Document revision history RM0046
934/936 Doc ID 16912 Rev 5
12-Mar-2012
4
cont’d
Chapter 21: LIN Controller (LINFlex)
Figure 237 (LIN status register (LINSR)): changed LINS access from read/write to write
only
Figure 242 (LIN output compare register (LINOCR)): changed note from
LINTCSR[LTOM] = 1 to LINTCSR[LTOM] = 0
Updated Section , Identifier filter enable register (IFER):
Figure 251 (Identifier filter enable register (IFER)): changed FACT field from 8 bit to 16
bit
Updated Table 254 (IFER field descriptions)
Removed “IFER[FACT] configuration“ table
Figure 254 (Identifier filter control register (IFCR2n)): changed ID access from read/write
“w1c’ to read/write only in initialization mode
Figure 255 (Identifier filter control register (IFCR2n + 1)): changed ID access from
read/write “w1c’ to read/write only in initialization mode
Added Section , Overrun
Section , Data transmission (transceiver as publisher): changed BDAR register with BDR
register
Reworded Section , Overrun
Section , Filter mode: changed sentence “eight IFCR registers” with “sixteen IFCR
registers“
Section , Identifier filter mode configuration: changed sentence “the filter must first be
deactivated by programming IFER[FACT] = 0“ with “the filter must first be activated by
programming IFER[FACT] = 1“
Section , Automatic resynchronization method now is a section
Section , LIN timeout mode: changed sentence “Setting the LTOM bit“ with “Resetting the
LTOM bit“
Section , Output compare mode: changed sentence “Programming LINTCSR[LTOM] = 0
enables the output compare mode“ with “Programming LINTCSR[LTOM] = 1 enables
the output compare mode“
Chapter 23: Analog-to-Digital Converter (ADC):
Renamed section “Analog watchdog pulse width modulation bus“ with Section , Analog
watchdog functionality, and reworded the section
Section 23.3.7, Interrupts: removed sentence “Interrupts can be individually enabled on a
channel by channel basis by programming the CIMR (Channel Interrupt Mask
Register).“
Section 23.3.8, Power-down mode: replaced sentence: “If the CTU is enabled and the
CSR[CTUSTART] bit is ‘1’, then the MCR[PWDN] bit cannot be set.“ with “If the CTU
is enabled and the MSR[CTUSTART] bit is ‘1’, then the MCR[PWDN] bit cannot be set.“
Table 294 (ADC digital registers): removed CIMR0 register, set address as reserved.
Removed “Channel Interrupt Mask Register (CIMR[0])“ section
Chapter 24: Cross Triggering Unit (CTU):
Figure 309 (Trigger Generator Sub-unit Input Selection Register (TGSISR)): converted
fields I14_FE and I14_RE to ‘Reserved’ and implemented fields I4_FE and I4_RE
Figure 316 (Trigger handler control register 1 (THCR1)): changed access type from read
only to read/write
Chapter 26: eTimer:
Section , Comparator Load register 1 (CMPLD1): Modified the description of CMPLD field
to read, “Specifies the preload value for the COMP1 register” instead of “Specifies the
preload value for the COMP2 register”.
Table 476. Revision history (continued)
Date Revision Changes
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