20.4.3 Interface Configuration ............................................................................................... 1463
20.5 Initialization and Configuration .................................................................................... 1464
20.5.1 Ethernet PHY Initialization .......................................................................................... 1465
20.6 Register Map ............................................................................................................ 1467
20.7 Ethernet MAC Register Descriptions ........................................................................... 1470
20.8 Ethernet PHY Register Descriptions ........................................................................... 1589
21 Universal Serial Bus (USB) Controller ............................................................. 1644
21.1 Block Diagram ........................................................................................................... 1645
21.2 Signal Description ..................................................................................................... 1645
21.3 Register Map ............................................................................................................ 1646
22 Analog Comparators .......................................................................................... 1653
22.1 Block Diagram ........................................................................................................... 1654
22.2 Signal Description ..................................................................................................... 1654
22.3 Functional Description ............................................................................................... 1655
22.3.1 Internal Reference Programming ................................................................................ 1656
22.4 Initialization and Configuration .................................................................................... 1658
22.5 Register Map ............................................................................................................ 1659
22.6 Register Descriptions ................................................................................................. 1659
23 Pulse Width Modulator (PWM) .......................................................................... 1669
23.1 Block Diagram ........................................................................................................... 1670
23.2 Signal Description ..................................................................................................... 1672
23.3 Functional Description ............................................................................................... 1672
23.3.1 Clock Configuration ................................................................................................... 1672
23.3.2 PWM Timer ............................................................................................................... 1672
23.3.3 PWM Comparators .................................................................................................... 1673
23.3.4 PWM Signal Generator .............................................................................................. 1674
23.3.5 Dead-Band Generator ............................................................................................... 1675
23.3.6 Interrupt/ADC-Trigger Selector ................................................................................... 1675
23.3.7 Synchronization Methods .......................................................................................... 1676
23.3.8 Fault Conditions ........................................................................................................ 1677
23.3.9 Output Control Block .................................................................................................. 1678
23.4 Initialization and Configuration .................................................................................... 1678
23.5 Register Map ............................................................................................................ 1679
23.6 Register Descriptions ................................................................................................. 1682
24 Quadrature Encoder Interface (QEI) ................................................................. 1748
24.1 Block Diagram ........................................................................................................... 1748
24.2 Signal Description ..................................................................................................... 1750
24.3 Functional Description ............................................................................................... 1750
24.4 Initialization and Configuration .................................................................................... 1753
24.5 Register Map ............................................................................................................ 1753
24.6 Register Descriptions ................................................................................................. 1754
25 Pin Diagram ........................................................................................................ 1771
26 Signal Tables ...................................................................................................... 1772
26.1 Signals by Pin Number .............................................................................................. 1773
26.2 Signals by Signal Name ............................................................................................. 1785
26.3 Signals by Function, Except for GPIO ......................................................................... 1797
26.4 GPIO Pins and Alternate Functions ............................................................................ 1808
June 18, 201410
Texas Instruments-Production Data
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