Tamper I/O Control
Up to four tamper I/Os are available. These signals are individually enabled and the detection level
can be configured per pin. Enabling the tamper IO will override all settings made in the GPIO module.
Each tamper IO has a weak pull-up.
Tamper Clocking
The Hibernate clock is the clock source for the Tamper module. When an external oscillator is used
and tamper is enabled, the external oscillator is monitored by the Tamper module. If the external
oscillator stops for any reason, the XOSCFAIL bit is set in the HIBTPSTAT register and the Hibernate
clock source is switched to the HIB LFIOSC immediately. When the XOSCST bit in the HIBTPSTAT
register is 0, indicating the external oscillator is active, a 1 can be written to the XOSCFAIL bit to
clear it and re-enable the external 32.768-kHz oscillator.
Note: Because the HIB LFIOSC has a wide frequency variation, it should not be configured as
the HIB clock source when accurate monitoring of the tamper logs are important.
Tamper Resets
The Tamper module uses the resets from the Hibernate module.
Important: The Hibernation module registers are reset under two conditions:
1. Any type of system reset (if the RTCEN and the PINWEN bits in the HIBCTL register
are clear and the TPEN bit in the HIBTPCTL register is clear).
2. A cold POR occurs when both the V
DD
and V
BAT
supplies are removed.
Any other reset condition is ignored by the Hibernation module.
7.3.7 Battery-Backed Memory
The Hibernation module contains 16 32-bit words of memory that are powered from the battery or
an auxiliary power supply and therefore retained during hibernation. The processor software can
save state information in this memory prior to hibernation and recover the state upon waking. To
access the upper eight words of memory, the processor must be in privilege mode. Refer to
“Processor Mode and Privilege Levels for Software Execution” on page 84 for more information
about processor privilege mode. The battery-backed memory can be accessed through the HIBDATA
registers. If both V
DD
and V
BAT
are removed, the contents of the HIBDATA registers are not retained.
7.3.8 Power Control Using HIB
Important: The Hibernation Module requires special system implementation considerations when
using HIB to control power, as it is intended to power-down all other sections of the
microcontroller. All system signals and power supplies that connect to the chip must
be driven to 0 V or powered down with the same regulator controlled by HIB.
The Hibernation module controls power to the microcontroller through the use of the HIB pin which
is intended to be connected to the enable signal of the external regulator(s) providing 3.3 V to the
microcontroller and other circuits. When the HIB signal is asserted by the Hibernation module, the
external regulator is turned off and no longer powers the microcontroller and any parts of the system
that are powered by the regulator. The Hibernation module remains powered from the V
BAT
supply
until a Wake event. Power to the microcontroller is restored by deasserting the HIB signal, which
causes the external regulator to turn power back on to the chip.
545June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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