Texas Instruments TM4C1294NCPDT - Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), Offset 0 X034

Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset
0x034
Each bit of the DMAALTCLR register represents the corresponding μDMA channel. Setting a bit
clears the corresponding SET[n] bit in the DMAALTSET register.
DMA Channel Primary Alternate Clear (DMAALTCLR)
Base 0x400F.F000
Offset 0x034
Type WO, reset -
16171819202122232425262728293031
CLR[n]
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
----------------Reset
0123456789101112131415
CLR[n]
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
----------------Reset
DescriptionResetTypeNameBit/Field
Channel [n] Alternate Clear
DescriptionValue
No effect.0
Setting a bit clears the corresponding SET[n] bit in the
DMAALTSET register meaning that channel [n] is using the
primary control structure.
1
Note: For Ping-Pong and Scatter-Gather cycle types, the µDMA
controller automatically sets these bits to select the alternate
channel control data structure.
-WOCLR[n]31:0
June 18, 2014724
Texas Instruments-Production Data
Micro Direct Memory Access (μDMA)