determined by the TnEVENT fields of the GPTMCTL register. During initialization in down-count
mode, the GPTMTnMATCHR and GPTMTnPMR registers are configured so that the difference
between the value in the GPTMTnILR and GPTMTnPR registers and the GPTMTnMATCHR and
GPTMTnPMR registers equals the number of edge events that must be counted. In up-count mode,
the timer counts from 0x0 to the value in the GPTMTnMATCHR and GPTMTnPMR registers. Note
that when executing an up-count, that the value of GPTMTnPR and GPTMTnILR must be greater
than the value of GPTMTnPMR and GPTMTnMATCHR. Table 13-7 on page 963 shows the values
that are loaded into the timer registers when the timer is enabled.
Table 13-7. Counter Values When the Timer is Enabled in Input Edge-Count Mode
Count Up ModeCount Down ModeRegister
0x0GPTMTnPR in combination with GPTMTnILRGPTMTnR
0x0GPTMTnPR in combination with GPTMTnILRGPTMTnV
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements or increments the counter by 1 until
the event count matches GPTMTnMATCHR and GPTMTnPMR. When the counts match, the GPTM
asserts the CnMRIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register, and holds it until
it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register. If the capture mode match
interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets the
CnMMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register. In up-count mode, the
current count of the input events is held in both the GPTMTnR and GPTMTnV registers. In
down-count mode, the current count of the input events can be obtained by subtracting the GPTMTnR
or GPTMTnV from the value made up of the GPTMTnPR and GPTMTnILR register combination.
In addition to generating interrupts, an ADC and/or a μDMA trigger can be generated. The ADC
trigger is enabled by setting the TnOTE bit in GPTMCTL and the event that activates the ADC is
configured in the GPTM ADC Event (GPTMADCEV) register. The μDMA trigger is enabled by
configuring and enabling the appropriate μDMA channel as well as the type of trigger enable in the
GPTM DMA Event (GPTMDMAEV) register. See “Channel Configuration” on page 683.
After the match value is reached in down-count mode, the counter is then reloaded using the value
in GPTMTnILR and GPTMTnPR registers, and stopped because the GPTM automatically clears
the TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events
are ignored until TnEN is re-enabled by software. In up-count mode, the timer is reloaded with 0x0
and continues counting.
Figure 13-2 on page 964 shows how Input Edge-Count mode works. In this case, the timer start
value is set to GPTMTnILR =0x000A and the match value is set to GPTMTnMATCHR =0x0006 so
that four edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted because the timer automatically clears the TnEN bit
after the current count matches the value in the GPTMTnMATCHR register.
963June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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