Texas Instruments TM4C1294NCPDT - Register 15: DMA Channel Enable Clear (DMAENACLR), Offset 0 X02 C

Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C
Each bit of the DMAENACLR register represents the corresponding µDMA channel. Setting a bit
clears the corresponding SET[n] bit in the DMAENASET register.
DMA Channel Enable Clear (DMAENACLR)
Base 0x400F.F000
Offset 0x02C
Type WO, reset -
16171819202122232425262728293031
CLR[n]
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
----------------Reset
0123456789101112131415
CLR[n]
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
----------------Reset
DescriptionResetTypeNameBit/Field
Clear Channel [n] Enable Clear
DescriptionValue
No effect.0
Setting a bit clears the corresponding SET[n] bit in the
DMAENASET register meaning that channel [n] is disabled for
μDMA transfers.
1
Note: The controller disables a channel when it completes the μDMA
cycle.
-WOCLR[n]31:0
June 18, 2014722
Texas Instruments-Production Data
Micro Direct Memory Access (μDMA)