Register 30: Ethernet MAC Transmit Frame Count for Frames Transmitted
after Multiple Collisions (EMACTXCNTMCOL), offset 0x150
This register maintains the number of successfully transmitted frames after multiple collisions in the
half-duplex mode.
Note: This counter is reset to all zeros by setting the CNTRST bit in the Ethernet MAC MMC
Control (EMACMMCCTRL), offset 0x100.
Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions (EMACTXCNTMCOL)
Base 0x400E.C000
Offset 0x150
Type RO, reset 0x0000.0000
16171819202122232425262728293031
TXMULTCOLG
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TXMULTCOLG
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
This field indicates the number of successfully transmitted frames after
multiple collisions in the half-duplex mode.
0x0ROTXMULTCOLG31:0
1525June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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