Error Handling
If the RX FIFO is full before it receives the EOF data from the MAC, an overflow is declared, the
entire frame (including the status word) is dropped and the Ethernet MAC Missed Frame and
Buffer Overflow Counter (EMACMFBOC) register is incremented. These error actions occur even
if the FEF bit is set in the EMACDMAPOPMODE register. If the start address of such a frame has
already been transferred to the TX/RX Controller, the rest of the frame is dropped and a dummy
EOF is written to the FIFO along with its status word. The descriptor status indicates a partial frame
because of overflow. In such frames, the Frame Length (FL) field in the receive descriptor is invalid.
If the RX FIFO is configured to operate in the store-and-forward mode and if the length of the received
frame is more than the FIFO size, overflow occurs and all such frames are dropped. During error
handling, the DMA flushes the error frame currently being read.
The Receive control logic can filter error and undersized frames if enabled through configuring the
FEF or FUF bit of the EMACDMAOPMODE register. Filtering must be set before the start address
of the frame has been transferred to the TX/RX controller for it to take effect.
Receive Word Status
At the end of an Ethernet frame transfer to the system memory, the TX/RX Controller sends a receive
status word, RDES0, to the application. Until the end of the frame transfer, the TX/RX Controller
stores the status and frame length in an asynchronous status FIFO whose depth is determined by
the size of the RX FIFO (2K) and the minimum size of the frame. If the frame size if 64, then the
asynchronous FIFO depth is 2048/64 = 32 bytes in length. Note that when the status of a partial
frame (because of overflow) is sent to the application, the Frame Length field of RDES0 is not valid
and is set to zero.
Note: When the timestamp feature is enabled, the receive status field is greater than 32-bits. An
extended status bit-field [63:32] provides information about the received Ethernet payload
when it is carrying PTP packets or TCP/UDP/ICMP over IP packets. Since the data bus is
32 bits, the status is transferred over two clock cycles.
20.3.3.3 MAC Flow Control
Flow control mechanisms can be enabled for both the TX and RX FIFO datapath, depending on the
configurations in the Ethernet MAC Flow Control (EMACFLOWCTL) register at offset 0x018 and
the DUPM bit configuration in the Ethernet MAC Configuration (EMACCFG) register at offset 0x000.
Table 20-16. TX MAC Flow Control
DescriptionDUPM bit in
EMACCFG
TFE bit in
EMACFLOWCTL
The MAC transmitter does not perform the flow control or backpressure
operation.
X0
The MAC transmitter performs backpressure when the FCBBPA bit in the
Ethernet MAC Flow Control (EMACFLOWCTL) register is set.
01
The MAC transmitter sends a pause frame when the FCBBPA bit in the Ethernet
MAC Flow Control (EMACFLOWCTL) register is set.
11
Table 20-17. RX MAC Flow Control
DescriptionDUPM bit in
EMACCFG
TFE bit in
EMACFLOWCTL
The MAC receiver does not detect the received Pause frames.X0
The MAC receiver does not detect the received Pause frames but recognizes
such frames as Control frames.
01
1437June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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