Texas Instruments TM4C1294NCPDT User Manual

Register 24: I
2
C FIFO Control (I2CFIFOCTL), offset 0xF04
The FIFO Control Register can be programmed to control various aspects of the FIFO transaction,
such as RX and TX FIFO assignment, byte count value for FIFO triggers and flushing of the FIFOs.
I2C FIFO Control (I2CFIFOCTL)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
I2C 6 base: 0x400C.2000
I2C 7 base: 0x400C.3000
I2C 8 base: 0x400B.8000
I2C 9 base: 0x400B.9000
Offset 0xF04
Type RW, reset 0x0004.0004
16171819202122232425262728293031
RXTRIGreserved
DMARXENA
RXFLUSH
RXASGNMT
RWRWRWRORORORORORORORORORORWRWRWType
0010000000000000Reset
0123456789101112131415
TXTRIGreserved
DMATXENA
TXFLUSH
TXASGNMT
RWRWRWRORORORORORORORORORORWRWRWType
0010000000000000Reset
DescriptionResetTypeNameBit/Field
RX Control Assignment
DescriptionValue
RX FIFO is assigned to Master0
RX FIFO is assigned to Slave1
0RWRXASGNMT31
RX FIFO Flush
Setting this bit will Flush the RX FIFO. This bit will self-clear when the
flush has completed.
0RWRXFLUSH30
DMA RX Channel Enable
DescriptionValue
DMA RX channel disabled0
DMA RX channel enabled1
0RWDMARXENA29
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved28:19
June 18, 20141350
Texas Instruments-Production Data
Inter-Integrated Circuit (I
2
C) Interface

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English