Register 89: Ethernet PHY MII Interrupt Status 2 - MR19 (EPHYMISR2), address
0x013
This register contains additional event status and enables for the interrupt function. If an event has
occurred since the last read of this register, the corresponding status bit is set. If the corresponding
enable bit in the register is set, an interrupt is generated if the event occurs. The INTEN bit (bit 1)
in the EPHYSCR register (PHY offset 0x011) must also be set to allow interrupts. The status
indications in this register are set even if the interrupt is not enabled.
Ethernet PHY MII Interrupt Status 2 - MR19 (EPHYMISR2)
Base n/a
Address 0x013
Type RW, reset 0x0000
0123456789101112131415
JABBERENPOLINTEN
SLEEPENMDICOEN
LBFIFOENPAGERXEN
ANERRENreservedJABBERPOLINTSLEEPMDICOLBFIFOPAGERXANERRreserved
RORWRWRWRWRWRWROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15
Auto-Negotiation Error Interrupt
Reading this bit clears the interrupt.
DescriptionValue
No Auto-negotiation error event pending.0
Auto-negotiation error interrupt is pending.1
0ROANERR14
Page Receive Interrupt
Reading this bit clears the interrupt.
DescriptionValue
Page has not been received.0
Page has been received.1
0ROPAGERX13
Loopback FIFO Overflow/Underflow Event Interrupt
Reading this bit clears the interrupt.
DescriptionValue
No FIFO Overflow/Underflow event pending.0
FIFO Overflow/Underflow event interrupt pending.1
0ROLBFIFO12
MDI/MDIX Crossover Status Changed Interrupt
Reading this bit clears the interrupt.
DescriptionValue
MDI crossover status has not changed.0
MDI crossover status changed interrupt is pending.1
0ROMDICO11
1625June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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