DescriptionResetTypeNameBit/Field
SRAM Sleep/Deep-Sleep Standby Mode Present
This bit determines whether the SRAMPM field in the SLPPWRCFG and
DSLPPWRCFG registers can be configured to put the SRAM into
Standby mode while in Sleep or Deep-Sleep mode.
DescriptionValue
A value of 0x1 in the SRAMPM fields is ignored.0
The SRAMPM fields can be configured to put the SRAM into
Standby mode while in Sleep or Deep-Sleep mode.
1
0x1ROSRAMSM11
SRAM Sleep/Deep-Sleep Low Power Mode Present
This bit determines whether the SRAMPM field in the SLPPWRCFG and
DSLPPWRCFG registers can be configured to put the SRAM into Low
Power mode while in Sleep or Deep-Sleep mode.
Refer to “Sleep Modes” on page 1843 for information regarding wake times
from Sleep and Deep-Sleep.
DescriptionValue
A value of 0x3 in the SRAMPM fields is ignored.0
The SRAMPM fields can be configured to put the SRAM into Low
Power mode while in Sleep or Deep-Sleep mode.
1
0x1ROSRAMLPM10
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved9
Flash Memory Sleep/Deep-Sleep Low Power Mode Present
This bit determines whether the FLASHPM field in the SLPPWRCFG
and DSLPPWRCFG registers can be configured to put the Flash memory
into Low Power mode while in Sleep or Deep-Sleep mode.
Refer to “Sleep Modes” on page 1843 for information regarding wake times
from Sleep and Deep-Sleep.
DescriptionValue
A value of 0x2 in the FLASHPM fields is ignored.0
The FLASHPM fields can be configured to put the Flash memory
into Low Power mode while in Sleep or Deep-Sleep mode.
1
0x1ROFLASHLPM8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved7:6
Automatic LDO Sequence Control Present
This bit indicates that the ability to sequence the LDO output voltage is
available during Sleep and Deep-Sleep modes.
DescriptionValue
Software cannot set the VADJEN bit in the LDOSPCTL and
LDODPCTL registers.
0
Software can set the VADJEN bit in the LDOSPCTL and
LDODPCTL registers.
1
0x1ROLDOSEQ5
287June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller