Register 154: Ethernet PHY Power Control (PCEPHY), offset 0x930
The PCEPHY register controls the power applied to the EEPROM module. The function of this bit
depends on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the
corresponding bits in the RCGCEPHY, SCGCEPHY and DCGCEPHY registers. If the Rn, Sn, or
Dn bit of the respective RCGCEPHY, SCGCEPHY and DCGCEPHY registers is 1 and the device
is in that mode, the module is powered and receives a clock irrespective of what the corresponding
Pn bit in the PCEPHY register is.
However, if the Rn, Sn, or Dn bit of the respective RCGCEPHY, SCGCEPHY and DCGCEPHY
registers is 0 and the device is in that mode, then the module behaves differently depending on the
value of the corresponding Pn bit in the PCEPHY register. In this case, when the Pn bit is clear the
module is not powered and does not receive a clock. If the Pn bit is set, the module is powered but
does not receive a clock. The table below details the differences.
Table 5-26. Module Power Control
DescriptionPnRn, Sn or Dn Value in
Respective RCGCx,
SCGCx, or DCGCx
Register
Module is not powered and does not receive a clock. In this case, the peripheral's
state is not retained.
This is the lowest power consumption state of any peripheral since it consumes no
dynamic nor leakage current. Hardware should perform a peripheral reset if the active
mode changes and the RCGCx, SCGCx, or DCGCx register is a 1 or the P0 bit is
changed to a 1.
Software must re-initialize the peripheral when re-enabled due to the loss of state.
00
Module is powered, but does not receive a clock.
In this case, the peripheral is inactive. This is the second-lowest power consumption
of any peripheral since it consumes only leakage current.
10
Module is powered and receives a clock.X1
Note: The Ethernet PHY module is not powered up at reset to prevent an automatic negotiation
on power-up. To properly initialize the PHY, first inhibit the PHY from running on power up
by setting the PHYHOLD bit in the Ethernet Peripheral Configuration (EMACPC) register
and then set the P0 bit in the PCEPHY register. Once it is determined that the PHY is ready
(by polling the R0 bit in the Peripheral Ready (PREPHY) register), the PHY can be
programmed with its appropriate values.
Note: If the MOSC is chosen as the clock to the Ethernet PHY then software has to enable the
MOSC before enabling the Ethernet PHY by setting the P0 bit in the PCEPHY.
Ethernet PHY Power Control (PCEPHY)
Base 0x400F.E000
Offset 0x930
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
P0reserved
RWROROROROROROROROROROROROROROROType
0000000000000000Reset
June 18, 2014478
Texas Instruments-Production Data
System Control
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