Register 3: Hibernation RTC Load (HIBRTCLD), offset 0x00C
This register is used to load a 32-bit value loaded into the RTC counter. The load occurs immediately
upon this register being written. When this register is written, the 15-bit sub seconds counter is also
cleared.
Note: This register is protected from errant code by using the HIBLOCK register. This register is
write-only; any reads to this register read back as zeros.
Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the WRC bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 535. The HIBIO register and bits RSTWK, PADIOWK and
WC of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL
register has been set may produce unexpected results.
Hibernation RTC Load (HIBRTCLD)
Base 0x400F.C000
Offset 0x00C
Type WO, reset 0x0000.0000
16171819202122232425262728293031
RTCLD
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
0000000000000000Reset
0123456789101112131415
RTCLD
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
RTC Load
A write loads the current value into the RTC counter (RTCC).
A read returns the 32-bit load value.
0x0000.0000WORTCLD31:0
June 18, 2014556
Texas Instruments-Production Data
Hibernation Module
To Next Page
Loading...
Need help?
General
