Register 28: EPI Write FIFO Count (EPIWFIFOCNT), offset 0x204
This register contains the number of slots currently available in the WFIFO. This register may be
used for polled writes to avoid stalling and for blocking reads to avoid excess stalling (due to
undrained writes). An example use for writes may be:
for (idx = 0; idx < cnt; idx++) {
while (EPIWFIFOCNT == 0) ;
*ext_ram = *mydata++;
}
The above code ensures that writes to the address mapped location do not occur unless the WFIFO
has room. Although polling makes the code wait (spinning in the loop), it does not prevent interrupts
being serviced due to bus stalling.
EPI Write FIFO Count (EPIWFIFOCNT)
Base 0x400D.0000
Offset 0x204
Type RO, reset 0x0000.0004
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
WTAVreserved
ROROROROROROROROROROROROROROROROType
0010000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:3
Available Write Transactions
The number of write transactions available in the WFIFO.
When clear, a write is stalled waiting for a slot to become free (from a
preceding write completing).
0x4ROWTAV2:0
905June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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