Register 8: QSSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
QSSI Masked Interrupt Status (SSIMIS)
QSSI0 base: 0x4000.8000
QSSI1 base: 0x4000.9000
QSSI2 base: 0x4000.A000
QSSI3 base: 0x4000.B000
Offset 0x01C
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RORMISRTMISRXMISTXMIS
DMARXMISDMATXMIS
EOTMISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:7
End of Transmit Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to the transmission of
the last data bit.
1
This bit is cleared when a 1 is written to the EOTIC bit in the SSI
Interrupt Clear (SSIICR) register.
0ROEOTMIS6
QSSI Transmit DMA Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to the completion of
the transmit DMA.
1
This bit is cleared when a 1 is written to the DMATXIC bit in the SSI
Interrupt Clear (SSIICR) register.
0RODMATXMIS5
QSSI Receive DMA Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to the completion of
the receive DMA.
1
This bit is cleared when a 1 is written to the DMARXIC bit in the SSI
Interrupt Clear (SSIICR) register.
0RODMARXMIS4
1257June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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