Register 166: Micro Direct Memory Access Peripheral Ready (PRDMA), offset
0xA0C
The PRDMA register indicates whether the μDMA module is ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCDMA bit is changed from 0 to 1. A Run mode clocking change is initiated if
the corresponding RCGCDMA bit is changed. A reset change is initiated if the corresponding SRDMA
bit is changed from 0 to 1.
The PRDMA bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Micro Direct Memory Access Peripheral Ready (PRDMA)
Base 0x400F.E000
Offset 0xA0C
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
R0reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:1
μDMA Module Peripheral Ready
DescriptionValue
The μDMA module is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
0
The μDMA module is ready for access.1
0ROR00
June 18, 2014502
Texas Instruments-Production Data
System Control
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