Register 67: Ethernet MAC Peripheral Configuration Register (EMACPC),
offset 0xFC4
The Ethernet MAC Peripheral Configuration Register (EMACPC) register configures the MAC
and PHY reset and interface parameters.
Ethernet MAC Peripheral Configuration Register (EMACPC)
Base 0x400E.C000
Offset 0xFC4
Type RW, reset 0x0080.040E
16171819202122232425262728293031
FASTLDMODETDRRUNLRR
ISOMIILLRXERIDLE
NIBDETDISDIGRESTART
reservedPINTFSPHYEXT
RWRWRWRWRWRWRWRWRORWRORORWRWRWRWType
0000000100000000Reset
0123456789101112131415
PHYHOLDANMODEANENFASTANSEL
FASTANEN
EXTFD
FASTLUPDFASTRXDV
MDIXEN
FASTMDIXRBSTMDIX
MDISWAPPOLSWAP
FASTLDMODE
RWRWRWRWRWRWRWRWRWRWRWRORWRWRWRWType
0301000000100000Reset
DescriptionResetTypeNameBit/Field
PHY Select
This bit is used to select whether the internal or an external PHY is used.
DescriptionValue
Internal PHY0
External PHY1
0RWPHYEXT31
Ethernet Interface Select
This field selects the PHY interface used by the MAC.
This input is sampled during reset and an update to this register field
must result in the MAC undergoing a reset event.
This field has the following encoded values:
DescriptionValue
MII (default) Used for internal PHY or external PHY connected
via MII.
0x0
reserved0x1-0x3
RMII: Used for external PHY connected via RMII.0x4
reserved0x5-0x7
0RWPINTFS30:28
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved27:26
PHY Soft Restart
This bit allows the user to restart the PHY. Asserting this bit causes the
PHY logic and internal register to reset to initial conditions. This bit does
not affect the configuration bits provided by the EMACPC register, which
are stored in the PHY following a chip reset. To initiate the soft reset to
the PHY, this bit must be written to a 1 and written again to a 0.
0RWDIGRESTART25
June 18, 20141582
Texas Instruments-Production Data
Ethernet Controller
To Next Page
Loading...
Need help?
General
