Table 10-8. GPIO Pins With Special Considerations .............................................................. 770
Table 10-9. GPIO Pins With Special Considerations .............................................................. 776
Table 10-10. GPIO Pins With Special Considerations .............................................................. 778
Table 10-11. GPIO Pins With Special Considerations .............................................................. 781
Table 10-12. GPIO Pins With Special Considerations .............................................................. 787
Table 10-13. GPIO Drive Strength Options .............................................................................. 800
Table 11-1. External Peripheral Interface Signals (128TQFP) ................................................. 817
Table 11-2. EPI Interface Options ......................................................................................... 822
Table 11-3. EPI SDRAM x16 Signal Connections .................................................................. 823
Table 11-4. CSCFGEXT + CSCFG Encodings ...................................................................... 827
Table 11-5. Dual- and Quad- Chip Select Address Mappings ................................................. 828
Table 11-6. Chip Select Configuration Register Assignment ................................................... 829
Table 11-7. Capabilities of Host Bus 8 and Host Bus 16 Modes .............................................. 829
Table 11-8. EPI Host-Bus 8 Signal Connections .................................................................... 831
Table 11-9. EPI Host-Bus 16 Signal Connections .................................................................. 833
Table 11-10. PSRAM Fixed Latency Wait State Configuration .................................................. 838
Table 11-11. Data Phase Wait State Programming .................................................................. 843
Table 11-12. EPI General-Purpose Signal Connections ........................................................... 849
Table 11-13. External Peripheral Interface (EPI) Register Map ................................................. 854
Table 11-14. CSCFGEXT + CSCFG Encodings ...................................................................... 880
Table 11-15. CSCFGEXT + CSCFG Encodings ...................................................................... 886
Table 12-1. Endian Configuration ......................................................................................... 947
Table 12-2. Endian Configuration with Bit Reversal ................................................................ 947
Table 12-3. CCM Register Map ............................................................................................ 949
Table 13-1. Available CCP Pins ............................................................................................ 956
Table 13-2. General-Purpose Timers Signals (128TQFP) ....................................................... 957
Table 13-3. General-Purpose Timer Capabilities .................................................................... 958
Table 13-4. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 960
Table 13-5. 16-Bit Timer With Prescaler Configurations ......................................................... 961
Table 13-6. Counter Values When the Timer is Enabled in RTC Mode .................................... 962
Table 13-7. Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 963
Table 13-8. Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 964
Table 13-9. Counter Values When the Timer is Enabled in PWM Mode ................................... 966
Table 13-10. Timeout Actions for GPTM Modes ...................................................................... 969
Table 13-11. Timers Register Map .......................................................................................... 974
Table 14-1. Watchdog Timers Register Map ........................................................................ 1031
Table 15-1. ADC Signals (128TQFP) .................................................................................. 1055
Table 15-2. Samples and FIFO Depth of Sequencers .......................................................... 1056
Table 15-3. Sample and Hold Width in ADC Clocks ............................................................. 1058
Table 15-4. R
S
and F
CONV
Values with Varying N
SH
Values and F
ADC
= 16 MHz ..................... 1059
Table 15-5. R
S
and F
CONV
Values with Varying N
SH
Values and F
ADC
= 32 MHz ..................... 1059
Table 15-6. Differential Sampling Pairs ............................................................................... 1066
Table 15-7. ADC Register Map ........................................................................................... 1073
Table 15-8. Sample and Hold Width in ADC Clocks ............................................................. 1127
Table 15-9. Sample and Hold Width in ADC Clocks ............................................................. 1139
Table 15-10. Sample and Hold Width in ADC Clocks ............................................................. 1147
Table 16-1. UART Signals (128TQFP) ................................................................................ 1163
Table 16-2. Flow Control Mode ........................................................................................... 1169
19June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller