Register 19: EPI Read FIFO (EPIREADFIFO0), offset 0x070
Register 20: EPI Read FIFO Alias 1 (EPIREADFIFO1), offset 0x074
Register 21: EPI Read FIFO Alias 2 (EPIREADFIFO2), offset 0x078
Register 22: EPI Read FIFO Alias 3 (EPIREADFIFO3), offset 0x07C
Register 23: EPI Read FIFO Alias 4 (EPIREADFIFO4), offset 0x080
Register 24: EPI Read FIFO Alias 5 (EPIREADFIFO5), offset 0x084
Register 25: EPI Read FIFO Alias 6 (EPIREADFIFO6), offset 0x088
Register 26: EPI Read FIFO Alias 7 (EPIREADFIFO7), offset 0x08C
Important: This register is read-sensitive. See the register description for details.
This register returns the contents of the NBRFIFO or 0 if the NBRFIFO is empty. Each read returns
the data that is at the top of the NBRFIFO, and then empties that value from the NBRFIFO. The
alias registers can be used with the LDMIA instruction for more efficient operation (for up to 8
registers). See Cortex™-M3/M4 Instruction Set Technical User's Manual (literature number SPMU159)
for more information on the LDMIA instruction.
EPI Read FIFn (EPIREADFIFOn)
Base 0x400D.0000
Offset 0x070
Type RO, reset -
16171819202122232425262728293031
DATA
ROROROROROROROROROROROROROROROROType
----------------Reset
0123456789101112131415
DATA
ROROROROROROROROROROROROROROROROType
----------------Reset
DescriptionResetTypeNameBit/Field
Reads Data
This field contains the data that is at the top of the NBRFIFO. After being
read, the NBRFIFO entry is removed.
-RODATA31:0
June 18, 2014902
Texas Instruments-Production Data
External Peripheral Interface (EPI)
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