Figure 11-29. EPI Clock Operation, CLKGATE=1, WR2CYC=1
Clock
(EPI0S31)
WR
(EPI0S28)
Address
Data
11.5 Register Map
Table 11-13 on page 854 lists the EPI registers. The offset listed is a hexadecimal increment to the
register's address, relative to the base address of 0x400D.0000. Note that the EPI controller clock
must be enabled before the registers can be programmed (see page 386). There must be a delay
of 3 system clocks after the EPI module clock is enabled before any EPI module registers are
accessed.
Note: A write immediately followed by a read of the same register, may not return correct data. A
delay (instruction or NOP) must be inserted between the write and the read for correct
operation. Read-write does not have this issue, so use of read-write for clear of error interrupt
cause is not affected.
Note: For all versions of EPI, only WORD read and write accesses to registers are supported.
Table 11-13. External Peripheral Interface (EPI) Register Map
See
page
DescriptionResetTypeNameOffset
857EPI Configuration0x0000.0000RWEPICFG0x000
859EPI Main Baud Rate0x0000.0000RWEPIBAUD0x004
861EPI Main Baud Rate0x0000.0000RWEPIBAUD20x008
863EPI SDRAM Configuration0x82EE.0000RWEPISDRAMCFG0x010
865EPI Host-Bus 8 Configuration0x0008.FF00RWEPIHB8CFG0x010
870EPI Host-Bus 16 Configuration0x0008.FF00RWEPIHB16CFG0x010
876EPI General-Purpose Configuration0x0000.0000RWEPIGPCFG0x010
879EPI Host-Bus 8 Configuration 20x0008.0000RWEPIHB8CFG20x014
885EPI Host-Bus 16 Configuration 20x0008.0000RWEPIHB16CFG20x014
892EPI Address Map0x0000.0000RWEPIADDRMAP0x01C
895EPI Read Size 00x0000.0003RWEPIRSIZE00x020
896EPI Read Address 00x0000.0000RWEPIRADDR00x024
897EPI Non-Blocking Read Data 00x0000.0000RWEPIRPSTD00x028
895EPI Read Size 10x0000.0003RWEPIRSIZE10x030
June 18, 2014854
Texas Instruments-Production Data
External Peripheral Interface (EPI)
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