Register 20: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048
Register 21: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088
Register 22: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8
Register 23: PWM3 Raw Interrupt Status (PWM3RIS), offset 0x108
These registers provide the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (PWM0RIS controls the PWM generator 0
block, and so on). If a bit is set, the event has occurred; if a bit is clear, the event has not occurred.
Bits in this register are cleared by writing a 1 to the corresponding bit in the PWMnISC register.
PWMn Raw Interrupt Status (PWMnRIS)
PWM0 base: 0x4002.8000
Offset 0x048
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INTCNTZEROINTCNTLOAD
INTCMPAUINTCMPADINTCMPBUINTCMPBD
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:6
Comparator B Down Interrupt Status
DescriptionValue
An interrupt has not occurred.0
The counter has matched the value in the PWMnCMPB register
while counting down.
1
This bit is cleared by writing a 1 to the INTCMPBD bit in the PWMnISC
register.
0ROINTCMPBD5
Comparator B Up Interrupt Status
DescriptionValue
An interrupt has not occurred.0
The counter has matched the value in the PWMnCMPB register
while counting up.
1
This bit is cleared by writing a 1 to the INTCMPBU bit in the PWMnISC
register.
0ROINTCMPBU4
June 18, 20141716
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
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