Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C
The GPIOICR register is the interrupt clear register. Writing a 1 to the DMAIC bit in this register
clears the corresponding interrupt bit in the GPIORIS and GPIOMIS registers. For edge-detect
interrupts, writing a 1 to the IC bit in the GPIOICR register clears the corresponding bit in the
GPIORIS and GPIOMIS registers. If the interrupt is a level-detect, the IC bit in this register has no
effect. In addition, writing a 0 to any of the bits in the GPIOICR register has no effect.
GPIO Interrupt Clear (GPIOICR)
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (AHB) base: 0x4006.0000
GPIO Port K (AHB) base: 0x4006.1000
GPIO Port L (AHB) base: 0x4006.2000
GPIO Port M (AHB) base: 0x4006.3000
GPIO Port N (AHB) base: 0x4006.4000
GPIO Port P (AHB) base: 0x4006.5000
GPIO Port Q (AHB) base: 0x4006.6000
Offset 0x41C
Type W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ICDMAICreserved
W1CW1CW1CW1CW1CW1CW1CW1CW1CROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:9
GPIO µDMA Interrupt Clear
DescriptionValue
The µDMA done interrupt is unaffected.0
The µDMA done interrupt is cleared.1
0W1CDMAIC8
GPIO Interrupt Clear
DescriptionValue
The corresponding interrupt is unaffected.0
The corresponding interrupt is cleared.1
0x00W1CIC7:0
769June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
To Next Page
Loading...
Need help?
General
