Register 27: GPIO Wake Pin Enable (GPIOWAKEPEN), offset 0x540
This register is used to configure K[7:4] as a wake enable source for the hibernation module. The
wake level must be programmed in the GPIOWAKELVL register at offset 0x544. In order for this
register configuration to become implemented, the WUUNLK bit needs to be set in the HIBIO register
at offset 0x02C in the hibernation module.
Note: This register is only available on Port K.
GPIO Wake Pin Enable (GPIOWAKEPEN)
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (AHB) base: 0x4006.0000
GPIO Port K (AHB) base: 0x4006.1000
GPIO Port L (AHB) base: 0x4006.2000
GPIO Port M (AHB) base: 0x4006.3000
GPIO Port N (AHB) base: 0x4006.4000
GPIO Port P (AHB) base: 0x4006.5000
GPIO Port Q (AHB) base: 0x4006.6000
Offset 0x540
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedWAKEP4WAKEP5WAKEP6WAKEP7reserved
RORORORORWRWRWRWROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:8
K[7] Wake Enable
DescriptionValue
Wake-on level is not enabled.0
Wake-on level is enabled.1
0RWWAKEP77
K[6] Wake Enable
DescriptionValue
Wake-on level is not enabled.0
Wake-on level is enabled.1
0RWWAKEP66
793June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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