Register 170: Synchronous Serial Interface Peripheral Ready (PRSSI), offset
0xA1C
The PRSSI register indicates whether the SSI modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCSSI bit is changed from 0 to 1. A Run mode clocking change is initiated if the
corresponding RCGCSSI bit is changed. A reset change is initiated if the corresponding SRSSI bit
is changed from 0 to 1.
The PRSSI bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Synchronous Serial Interface Peripheral Ready (PRSSI)
Base 0x400F.E000
Offset 0xA1C
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
R0R1R2R3reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:4
SSI Module 3 Peripheral Ready
DescriptionValue
SSI module 3 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
0
SSI module 3 is ready for access.1
0ROR33
SSI Module 2 Peripheral Ready
DescriptionValue
SSI module 2 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
0
SSI module 2 is ready for access.1
0ROR22
SSI Module 1 Peripheral Ready
DescriptionValue
SSI module 1 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
0
SSI module 1 is ready for access.1
0ROR11
507June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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