Register 10: UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit
allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit
prevents the raw interrupt signal from being sent to the interrupt controller.
Note: Registers that contain bits for modem control or status only apply to the following UARTs:
■ UART0 (modem flow control and modem status)
■ UART1 (modem flow control and modem status)
■ UART2 (modem flow control)
■ UART3 (modem flow control)
■ UART4 (modem flow control)
UART Interrupt Mask (UARTIM)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x038
Type RW, reset 0x0000.0000
16171819202122232425262728293031
DMARXIMDMATXIMreserved
RWRWROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RIIMCTSIMDCDIMDSRIMRXIMTXIMRTIMFEIMPEIMBEIMOEIMEOTIM9BITIMreserved
RWRWRWRWRWRWRWRWRWRWRWRWRWROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:18
Transmit DMA Interrupt Mask
DescriptionValue
The DMATXRIS interrupt is suppressed and not sent to the
interrupt controller.
0
An interrupt is sent to the interrupt controller when the
DMATXRIS bit in the UARTRIS register is set.
1
0RWDMATXIM17
June 18, 20141194
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
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