Register 33: USB Memory Power Control (USBMPC), offset 0x284
This register provides power control to the peripheral memory array.
Note: If the USBMPC register's PWRCTL field is set to 0x3 and the power domain to the USB is
turned off by writing a 0 to the P0 bit of the PCUSB register, then the SRAM memory goes
into retention and the MEMSTAT field of the USBPDS register reads as 0x1 (retention).
USB Memory Power Control (USBMPC)
Base 0x400F.E000
Offset 0x284
Type RW, reset 0x0000.0003
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PWRCTLreserved
RWRWROROROROROROROROROROROROROROType
1100000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:2
Memory Array Power Control
Allows multiple levels of power control in peripheral's SRAM memory
space
DescriptionValue
Array OFF0x0
SRAM Retention0x1
Reserved0x2
Array On0x3
0x3RWPWRCTL1:0
313June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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