Register 21: HIB Tamper Control (HIBTPCTL), offset 0x400
The Tamper Control (HIBTPCTL) register provides control of the module.
Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the WRC bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 535. The HIBIO register and bits RSTWK, PADIOWK and
WC of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL
register has been set may produce unexpected results.
Note: Errant writes to the Tamper registers are protected by the Hibernate HIBLOCK register.
HIB Tamper Control (HIBTPCTL)
Base 0x400F.C000
Offset 0x400
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TPENreservedTPCLRreservedMEMCLRreservedWAKEreserved
RWROROROW1CRORORORWRWRORWROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:12
Wake from Hibernate on a Tamper Event
DescriptionValue
Do not wake from hibernate on a tamper event.0
Wake from hibernate on a tamper event.1
0RWWAKE11
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved10
HIB Memory Clear on Tamper Event
DescriptionValue
Do not Clear HIB memory on tamper event.0x0
Clear Lower 32 Bytes of HIB memory on tamper event0x1
Clear upper 32 Bytes of HIB memory on tamper event0x2
Clear all HIB memory on tamper event0x3
0RWMEMCLR9:8
587June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller