When reading the Hibernation Calendar n (HIBCALn) registers, the status of the VALID bit in the
HIBCAL0/1 register must be checked to ensure the registers are in sync before reading.
The calendar function will keep track of the following:
■ Seconds (0-59 seconds)
■ Minutes (0-59 minutes)
■ Hours (0-23 or 0-11 hours with an AM/PM option)
■ Day of the week (0-6)
■ Day of the month (1-31 days)
■ Month (1-12 months)
■ Year (00-99 years)
The hours may be reported with AM/PM or 24-hour based on the CAL24 bit in the HIBCALCTL
register. The leap year compensation is handled within the calendar function. The number of days
in February are adjusted to 29 whenever the year is divisible by four.
RTC Calendar Match
The HIB Calendar Match function can be used to generate an interrupt on a match of seconds,
minutes, hours, and day of month. The day of the week, year and month are not included in the
match function. To ignore a match function for the hours, minutes, or seconds, set each of the upper
two bits to 1 in the respective fields of the HIBCALMn register. To ignore the day of the month, set
the DOM field to all zeros in the HIBCALM1 register. If a match occurs in any field, the RTCALT0 bit
is set in the HIBRIS register.
7.3.5.4 RTC Trim
The RTC counting rate can be adjusted to compensate for inaccuracies in the clock source by using
the predivider trim register, HIBRTCT. This register has a nominal value of 0x7FFF, and is used for
one second out of every 64 seconds in RTC counter mode, when bits [5:0] in the HIBRTCC register
change from 0x00 to 0x01, to divide the input clock. Trim is applied every 60 seconds in calendar
mode. This configuration allows the software to make fine corrections to the clock rate by adjusting
the predivider trim register up or down from 0x7FFF. The predivider trim should be adjusted up from
0x7FFF in order to slow down the RTC rate and down from 0x7FFF in order to speed up the RTC
rate.
Care must be taken when using trim values that are near to the sub seconds match value in the
HIBRTCSS register. It is possible when using trim values above 0x7FFF to receive two match
interrupts for the same counter value. In addition, it is possible when using trim values below 0x7FFF
to miss a match interrupt.
In the case of a trim value above 0x7FFF, when the RTCSSC value in the HIBRTCSS register reaches
0x7FFF, the RTCC value increments from 0x0 to 0x1 while the RTCSSC value is decreased by the
trim amount. The RTCSSC value is counted up again to 0x7FFF before rolling over to 0x0 to begin
counting up again. If the match value is within this range, the match interrupt is triggered twice. For
example, as shown in Figure 7-5 on page 542, if the match interrupt was configured with RTCM0=0x1
and RTCSSM=0x7FFD, two interrupts would be triggered.
541June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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